The present invention relates to a semiconductor memory device, especially to a semiconductor memory device which comprises a dual port memory cell.
In a semiconductor memory device which comprises a dual port memory cell, when a read or a write is performed from one port of a certain memory cell and subsequently a write is performed from the other port of the memory cell at the same address or in the same row of the layout, the subsequent write is affected by the previous read or the previous write; accordingly, the subsequent write may result in error.
Patent Document 1 (Japanese Patent Laid-open No. Hei 5 (1993)-109279) discloses the following technology to cope with such a problem. That is, Patent Document 1 discloses the technology in which, when plural word lines belonging to the same row are selected from plural ports for a read or a write, a short circuit is employed to short substantially a bit line corresponding to a port selected for the write among bit lines corresponding to the plural selected ports and another arbitrary selected bit line. Patent Document 1 describes that, by adopting such a configuration, the problem of an erroneous writing to a cell at the time of selecting the same row from plural ports is solved.    (Patent Document 1) Japanese Patent Laid-open No. Hei 5 (1993)-109279